TS-75XX Errata ramcorruption

From Technologic Systems Manuals (sandbox)
Synopsis Incorrect DDR-RAM timing causing RAM corruption
Severity High
Class Hardware bug
Affected TS-7500 FPGA rev 0x04 and below

TS-7550 FPGA rev 0x03 and below

TS-7552 FPGA rev 0x02 and below

TS-7553 FPGA rev 0x00

TS-4500 FPGA rev 0x02 and below

Status Workarounds available


One of the RAM timing registers has a value that is not completely compatible with our hardware layout. This bug has the ability to manifest single bit-flips at various temperatures and yet work correctly in another temperature range. This can cause issues with USB read/write (due to heavy DMA use), system instability, or system hangs (which by default results in a reboot due to the WDT). You can query your FPGA revision with the following command:

ts7500ctl -i


The permanent fix is to send back your SBC to us for reprogramming. There is a way however to modify the RAM timing register once the SBC is booted up and operational. The command:

devmem 0x72000030 32 0x22

Will put the correct timing value in the timing register, however, this leaves the SBC vulnerable to this corruption until the command is issued.