From Technologic Systems Manuals (sandbox)
Product Page
TS-ADC16/24 Library Users Guide
Linux Driver
Physical Characteristics
Weight: 71.4 Grams (approximate)

1 Overview

The TS-ADC24 is a 8-bit (16-bit in ARM mode) PC/104 peripheral board (standard format) that provides 24 12-bit ADC (analog to digital converter) channels with internal 512x16bit RAM-FIFO for data acquisition and analog applications.

The TS-ADC24 features two AD7266 chips with sampling rate up to 2msps each (mega samples per second), 4msps total. Each ADC chip provides 12 ADC channels, 12-bit wide each, which can be configured as 12 single ended channels or 6 differential channels. Each chip can take 2 samples at a time, allowing the board to simultaneously read 4 channels. Each sample takes about 1us to be read. 16 of the ADC channels are brought out using rugged removable screw terminal connectors. In addition, all the ADC channels can be accessed via two standard 26-pin jumper headers.

Features include:

  • Two AD7266 ADC chips
  • 24 channels 12-bit ADC
  • Sampling rate up to 4msps
  • Single ended or differential channels
  • Takes 4 samples simultaneously
  • Internal 512x16bit RAM-FIFO
  • Jumper selectable I/O and IRQ
  • PC/104 Dimensions 3.6 x 3.8 inches
  • RoHS compliant
  • Linux drivers available
  • Jumper selectable I/O an IRQ
  • PC/104 Dimensions 3.6 x 3.8 inches

2 Hardware Description

2.1 Jumpers

  • Jumpers 1 and 2 selects 1 of 4 IO address regions;
  • Jumper 3 ON selects ARM mode for interrupt sharing and 16-bit bus cycles using 64-pin PC/104 connector;
  • Jumper 4 OFF selects IRQ6; Jumper 4 ON selects IRQ7;

2.2 AD1 Header Pin-Out

  • ADC chip 1 has two internal ADC machines with 6 channels each: AD1 and AD3;
  • AD1-0 is channel 0 of the first ADC on chip 1;
  • AD2-0 is channel 0 of the second ADC on chip 1;
PIN-02 PIN-04 PIN-06 PIN-08 PIN-10 PIN-12 PIN-14 PIN-16 PIN-18 PIN-20 PIN-22 PIN-24 PIN-26
*PIN-01 PIN-03 PIN-05 PIN-07 PIN-09 PIN-11 PIN-13 PIN-15 PIN-17 PIN-19 PIN-21 PIN-23 PIN-25
ch. 0
ch. 4
ch. 8
ch. 12
ch. 16
ch. 20
ch. 2
ch. 6
ch. 10
ch. 14
ch. 18
ch. 22

2.3 AD2 Header Pin-Out

  • ADC chip 2 has two internal ADC machines with 6 channels each: AD2 and AD4;
  • AD2-0 is channel 0 of the first ADC on chip 2;
  • AD4-0 is channel 0 of the second ADC on chip 2;
PIN-02 PIN-04 PIN-06 PIN-08 PIN-10 PIN-12 PIN-14 PIN-16 PIN-18 PIN-20 PIN-22 PIN-24 PIN-26
*PIN-01 PIN-03 PIN-05 PIN-07 PIN-09 PIN-11 PIN-13 PIN-15 PIN-17 PIN-19 PIN-21 PIN-23 PIN-25
ch. 1
ch. 5
ch. 9
ch. 13
ch. 17
ch. 21
ch. 3
ch. 7
ch. 11
ch. 15
ch. 19
ch. 23

2.4 PC/104 IO Base Address

CPU board 8-bit IO 16-bit IO
TS-7200 series, TS-7300, TS-7400 0x11E00000 0x21E00000
TS-7350, TS-7370 0x600FF800 0x600FF800
TS-7800 series 0xEE000000 0xEF000000

2.5 Address Decode

JP1 JP2 IO Base Address
OFF OFF 0x100
ON OFF 0x120
OFF ON 0x140
ON ON 0x160

2.6 Register Map

Address Register Access Description
BASE+00 BID: Board ID register RO 15-12: Jumper status (jp4, jp3, jp2, jp1)
11-8: PLD Revision
7-0: Board ID = 0x3f
BASE+02 ADCCFG: ADC configuration register

*writing to bits 1-8 of this register causes the system to reset (resets FFCOUNT and FFHEAD). Bit 0 can be written anytime
RW 15:9: reserved
8: SEDIF Global single ended/differential (OR'ed with bit5)
0 – differential
1 – single ended (default)
7-6: IRNG Global Analog Input Range
00 – 0 to +Vref
01 – 0 to +2xVref (default)
10 – 0 to +2xVref
11 – 0 to +2xVref
5: SEDIF Global single ended/differential (OR'ed with bit8 to enable 8-bit systems compatibility)
0 – differential
1 – single ended (default)
4-1: NUMCHAN number of group of 4 channels (two from each chip) to be read in a single scan cycle, starting by channel 0, up to 5. 24 total channels can be read if numchan is 5.
0: SYSCOM/STAT system command/status bit
0 – stop system/system stopped
1 – start system/system running
BASE+04 ADCDLY_MSB: ADC delay RW 15-8: reserved
7-0: bits [23:16] 24-bit pacing clock counter
BASE+06 ADCDLY_LSB: ADC delay RW 15-0: bits [15:0] 24-bit pacing clock counter
BASE+08 ADCSTAT: ADC system status register RW 15-6: FFCOUNT[9:0] FIFO count

*bit 15 (FFCOUNT[9]) is the FFFULL bit and indicates FIFO full (1 yes/0 no)
*bit 14 (FFCOUNT[8]) is the FFHFULL bit and indicates FIFO half full or greater (1 yes/0 no)
*bits [15:6] are also a write-only regis3ter for the FIFO count value which triggers an interrupt if interrupt is enabled (bit INTEN). Default is FIFO half-full.

5-1: FFHEAD (RO) channel on the head of the FIFO
00000 – channel 1 ...
01111 – channel 16 ...
10111 – channel 24
0: INTEN interrupt enable for ADC
0 – disable (default)
1 – enable
BASE+0A ADCFIFO: FIFO for retrieving AD data RO 15: ADCCHIP current ADC chip for the data read
0 – data from ADC chip 1
1 – data from ADC chip 2
14-12: CURNUMCHAN current number of channel for the data read
11-0: 12-bit ADC data read
BASE+0C Reserved 15-0: reserved
BASE+0E Reserved 15-0: reserved
BASE+10 Reserved 15-0: reserved
BASE+12 Reserved 15-0: reserved
BASE+14 Reserved 15-0: reserved
BASE+16 Reserved 15-0: reserved
BASE+18 Reserved 15-0: reserved
BASE+1A ADCFIFO_LSB: LSB FIFO for retrieving AD data RO 7-0: LSB ADC data read
BASE+1B ADCFIFO_MSB: MSB FIFO for retrieving AD data RO 7-0: MSB ADC data read
BASE+1C Reserved 15-0: reserved
BASE+1E Reserved 15-0: reserved

3 Functional Specification

3.1 ADC Channels

  • FPGA scans ADC block of 4 channels (four channels simultaneously, two in each chip, from channel-pair 0 to channel-pair Reg.ADCCFG.NUMCHAN) as fast as it can (sampling cycle of one ADC channel takes about 1us), put data on the FIFO (Reg.ADCFIFO) and then wait 24-bit pacing clock (Reg.ADCDLY) to expire in order to start another sampling cycle;
  • Reading Reg.ADCFIFO or Reg.ADCFIFO_MSB retrieves ADC data out from the internal FIFO and update internal FIFO counters and pointers. Reg.ADCFIFO_LSB and Reg.ADCFIFO_MSB enable compatibility with 8-bit PC/104 systems;
  • 24-bit pacing clock=0 (Reg.ADCDLY) indicates continuous ADC scanning; 24-bit pacing clock!=0 indicates the amount of 32MHz clocks the system will wait before the next scan cycle starts;
  • The minimal acceptable value to be loaded for the pacing clock register is 1us, or hex 20;
  • Updating the pacing clock value requires stopping the system by writing 0 to Reg.ADCCFG.SYSCOM;
  • Interrupt signal is set high/low following the behavior of the write-only register FIFO count-interrupt (Reg.ADCSTAT.FFCOUNT[9:0], default is FIFO half-full), meaning that the CPU will be interrupted when FIFO count is equal to FIFO count-interrupt (or greater) and interrupt will be automatically cleared when FIFO is less than FIFO count-interrupt;
  • Interrupt generation is disabled by default and can be enabled via the enable bit Reg.ADCSTAT.INTEN;
  • Size of FIFO is statically defined at 512*16bit samples;
  • FIFO is half-full when FIFO_COUNT>=(512/2), FIFO is full when FIFO_COUNT=512;
  • Starting the system (Reg.ADCCFG.SYSCOM) will reset the FIFO_COUNT to zero and start scanning cycles;
  • Reg.ADCCFG.SYSCOM can also be used for system status read (running/stopped)
  • Stopping the system (Reg.ADCCFG.SYSCOM) will stop scanning cycles. After system stop, FIFO can still be read until it is empty or system is re-initialized;
  • If FIFO is full (Reg.ADCSTAT.FFFULL), then system status changes to stopped (Reg.ADCCFG.SYSSTAT), scan cycles are stopped and system waits until host restarts it via bit (Reg.ADCCFG.SYSCOM). The remaining data in the FIFO is available until the system is restarted;
  • Reg.ADCSTAT.FFHEAD is initialized at hex 0 when first word is written to the FIFO, then stepped by 1 whenever a word is pulled out from the FIFO by the host until it reaches Reg.ADCSTAT.NUNCHAN. Reg.ADCSTAT.FFHEAD is re-initialized at hex 0 when it is equal to Reg.ADCSTAT.NUNCHAN;
  • All the registers are 16-bit wide; registers can also be accessed as 8-bit registers; writing to a 16-bit register using 8-bit cycles requires the LSB to be written before the MSB in consecutive cycles;
  • In order to synchronize the internal machine and initialize the ADC chips after power up, it is recommended to perform an initialization cycle (Reg.ADCCFG.SYSCOM) before real utilization;
  • The on-board Green LED will blink whenever there is a read access to the internal ADC FIFO;
  • The selected range and input configuration determine the output configuration of the ADC. In single-ended mode in range 0-Vref, straight binary is used mapping 0V to 0 and Vref to 4095. In single-ended mode in range 0-2xVref, 2's compliment is used mapping 0V to -2048 and 2xVref to 2047. In differential mode for range 0-Vref, 2's compliment is used mapping 0V to 0, +Vref to 2047, and -Vref to -2048. Likewise in differential mode for range 0-2xVref, 2's compliment is used mapping 0V to 0, +2xVref to 2047, and -2xVref to -2048. See the datasheet for AD7266 pg. 17 for more details.

3.2 Software Support

3.3 Linux Shell Library

In order to correctly access the TS-ADC24 registers and make use of its functions, a Linux shell script library is provided. This library include routines for the ADC machine, DACs, counters, digital IO, etc. All the registers are handled using 8-bit PC/104 cycles, therefore the routines are compatible with both 8-bit and 16-bit systems. Make sure to use the right base address for 8-bit PC/104 IO cycles in your platform by editing the ISAIO8_BASE variable. A complete list of the commands available is below:

  • adc_status: Returns status of ADC machine
  • adc_start: Starts ADC machine
  • adc_restart: Re-starts ADC machine
  • adc_stop: Stops ADC machine
  • adc_sedif: Returns status of ADC single ended/differential
  • adc_set_sedif: Enables ADC single ended
  • adc_clr_sedif: Enables ADC differential
  • adc_inrng: Returns status of ADC input range
  • adc_set_inrng [0-3]: Sets input range to parameter
  • adc_inten: Returns status of interrupt enable
  • adc_set_inten: Enables interrupt
  • adc_clr_inten: Disables interrupts
  • adc_set_ffcountint [0-512]: Sets fifo count for interrupt to parameter
  • adc_numchan: Returns number of pair of ADC channels
  • adc_set_numchan [0-7]: Sets number of pair of ADC channels to parameter
  • adc_dly: Returns 24-bit ADC pacing clock
  • adc_set_dly [0-16777215]: Sets 24-bit ADC pacing clock to parameter
  • adc_fffull: Returns FIFO full status
  • adc_ffhfull: Returns FIFO half-full status
  • adc_ffcount: Returns FIFO count
  • adc_ffhead: Returns channel on the head of the FIFO
  • adc_fifo: Returns channel on the head of the FIFO with information
  • adc_fifoh: Returns channel on the head of the FIFO
  • adc_fifon [0-512]: Returns n channels from FIFO
  • adc_fifoall: Returns all channels from the FIFO
  • adc_fifocont: Returns all channels from the FIFO, reading continuously

To make the commands of the TS-ADC24 shell library available at a shell prompt, initiate a new shell process using the TS-ADC24 shell library file as the ENV variable. For example:

# export ENV=/tsadc.lib
# chroot /
# tsadchelp

Or simply source the TS-ADC24 shell library on your running shell program:

# . /tsadc.lib
# tsadchelp

3.3.1 Linux Driver


4 Product Notes

4.1 FCC Advisory

This equipment generates, uses, and can radiate radio frequency energy and if not installed and used properly (that is, in strict accordance with the manufacturer's instructions), may cause interference to radio and television reception. It has been type tested and found to comply with the limits for a Class A digital device in accordance with the specifications in Part 15 of FCC Rules, which are designed to provide reasonable protection against such interference when operated in a commercial environment. Operation of this equipment in a residential area is likely to cause interference, in which case the owner will be required to correct the interference at his own expense.

If this equipment does cause interference, which can be determined by turning the unit on and off, the user is encouraged to try the following measures to correct the interference:

Reorient the receiving antenna. Relocate the unit with respect to the receiver. Plug the unit into a different outlet so that the unit and receiver are on different branch circuits. Ensure that mounting screws and connector attachment screws are tightly secured. Ensure that good quality, shielded, and grounded cables are used for all data communications. If necessary, the user should consult the dealer or an experienced radio/television technician for additional suggestions. The following booklets prepared by the Federal Communications Commission (FCC) may also prove helpful:

How to Identify and Resolve Radio-TV Interference Problems (Stock No. 004-000-000345-4) Interface Handbook (Stock No. 004-000-004505-7) These booklets may be purchased from the Superintendent of Documents, U.S. Government Printing Office, Washington, DC 20402.

4.2 Limited Warranty

Technologic Systems warrants this product to be free of defects in material and workmanship for a period of one year from date of purchase. During this warranty period Technologic Systems will repair or replace the defective unit in accordance with the following process:

A copy of the original invoice must be included when returning the defective unit to Technologic Systems, Inc. This limited warranty does not cover damages resulting from lightning or other power surges, misuse, abuse, abnormal conditions of operation, or attempts to alter or modify the function of the product.

This warranty is limited to the repair or replacement of the defective unit. In no event shall Technologic Systems be liable or responsible for any loss or damages, including but not limited to any lost profits, incidental or consequential damages, loss of business, or anticipatory profits arising from the use or inability to use this product.

Repairs made after the expiration of the warranty period are subject to a repair charge and the cost of return shipping. Please, contact Technologic Systems to arrange for any repair service and to obtain repair charge information.